Many attempts have been made in the prior art to control and cancel interference caused by an external transmission system.
FIG. 1 is a block diagram to show a first prior art interference cancellation circuit. This is equivalent to the circuit disclosed in Japanese Patent Application Laid-open Sho 62-147881 (JPA Sho 60-287881).
A signal is (described herein as a digital signal) received by a main antenna 1 of a main signal receiver system and includes an interference signal from the other transmission system. The received signal is supplied to a frequency converter 3 via a band-pass filter 2 to be converted to an intermediate frequency (IF) band.
The signal which may cause the interference is received by an auxiliary antenna 4 directed at the interference source. The signal received by the auxiliary antenna 4 is passed to a band pass filter 5 for signal-to-noise ratio improvement and converted to the intermediate frequency band by a frequency converter 6 with the local oscillation frequency band by a converter 6 with the main signal side and is fed from a local oscillator 7.
The obtained interference signal from frequency converter 6 is adjusted in phase and amplitude by a variable phase shifter 8 and a variable attenuator 10 to produce a cancellation signal which is opposite in phase to but the same in amplitude as the interference signal component that is mixed in the main signal. By adding the cancellation signal by an combiner 11, the interference signal component mixed in the main signal can be cancelled.
In order to control the variable phase shifter 8 and the variable attenuator 10, error signals and interference signals are obtained for the in-phase and the quadrature phase components.
In order to detect the in-phase and the quadrature phase components of the interference signal component after it is added with remaining in the main signal even after it is added with cancellation signal by the combiner 11, the output from the combiner 11 is fed into a demodulator 12. A coherent quadrature phase detector comprising a 90 degree phase shifter 14 and two phase detectors 15, 16 is provided within the demodulator 12. The coherent quadrature phase detector detects the output from the combiner 11 by means of the local frequency 13 reproduced from the signal received on the main signal side and divides them into the in-phase component and the quadrature phase component, which in turn are supplied to error signal detectors 19, 20 via low-pass filters 17, 18. The error signal detectors 19, 20 detect the remaining interference signal component and generate error signals respectively indicative of the in-phase and the quadrature phase components.
Meanwhile, the interference signals which have passed through the variable phase shifter 8 are divided into two by a signal divider 9, one output of which is output into the variable attenuator 10 and the other to the coherent quadrature phase detector comprising a 90 degree phase shifter 26 and phase detectors 27, 28. The coherent phase detector divides the interference signal into the in-phase component and the quadrature phase component by means of the local frequency 13 reproduced by the demodulator 12 on the main signal side. Thus divided interference signals are supplied into decision circuits 31, 32 via low-pass filters 29, 30. The decision circuits 31, 32 digitize respectively the interference signals by using a timing signal obtained at the demodulator 12 for the main signal.
Since the description herein is being made using an example of digital processing, it becomes necessary to use decision circuits 31, 32 for digitizing. No such digitizing is necessary in the case of analog processing.
When the outputs from the error signal detectors 19, 20 are in the form of digital signals, an analog/digital converter may be used. In such a case, if the main signal is one of the 16QAM type, the demodulated signal becomes quaternary, and it is sampled by an analog/digital converter having three or more bits of output. The table below shows the digital output therefrom. The digital output shows the result of decision in the most and next significant bits and the direction of error in the third bit. Therefore, the output in the third bit is used as an error signal. The most significant bit is used as a polarity signal.
TABLE ______________________________________ analog input (quaternary digital output signal) MSB 2nd bit 3rd bit ______________________________________ high level . ---- 1 1 0 1 . ----- 1 0 0 1 1 . ---- 0 0 . ---- 1 low level 0 0 ______________________________________
Correlation between thus obtained error signals and the interference signals in their in-phase and quadrature phase components are then obtained.
An exclusive OR operation is performed between their quadrature phase components and in phase components by exclusive OR circuits 34, 35, and their outputs are supplied to an integrator 43 via resistors 38, 39. The output from integrator 43 is used as a control signal for the variable attenuator 10. The exclusive OR operation between the in-phase components and the quadrature phase components are obtained by the exclusive OR circuits 36, 37 and their outputs are supplied to an integrator 42 via resistors 40, 41 and the output from the integrator 42 is used as a control signal for the variable phase shifter 8.
FIG. 2 is a block diagram to show the second prior art device, the circuit of which is equivalent to the circuit disclosed in Japanese Patent Application Laid-open Sho 62- (JPA Sho 61-75555) wherein the variable phase shifter 8 and the variable attenuator 10 in the first prior art circuit are replaced with a quadrature amplitude modulator 51.
The quadrature amplitude modulator 51 comprises a signal divider 52 which divides a signal into two paths, a phase shifter 53 which shifts the phase of one of the divided signals by 90 degrees, a bipolar attenuator 54 which receives as input the signal passing through the phase shifter 53, a bipolar attenuator 55 which receives as input the other output signals from the divider 52, and a combiner 56 which adds the outputs from the two bipolar attenuators 54, 55. The quadrature amplitude modulator 51 is fed with the interference signals which are received on the side of the auxiliary antenna 4 and divided by a signal divider 50.
The method of controlling the two bipolar attenuators 54, 55 will be explained below.
The signal combined by the combiner 11 is input at the demodulator 12. The input signal is detected in quadrature phase by phase detectors 15, 16 in the demodulator 12 by means of the local frequency 13 reproduced from the signals received by the main signal side. The detector outputs are passed through low-pass filters 17, 18 to be taken out as a baseband signal of the in-phase and the quadrature phase components. These baseband signals are supplied into the error signal detectors 19, 20 to detect remaining interference signal interference signal components.
Meanwhile, the interference signal converted into the IF band is detected in quadrature phase by phase detectors 27, 28, and each signal is passed to decision circuits 31, 32 via low-pass filters 29, 30. The decision circuits 31, 32 digitize respective input signals by using clock signal 44 obtained by a demodulator 12 to obtain binary interference signals for the quadrature component and the in-phase component.
Correlations are then obtained between error signals of the main signals in the in-phase and the quadrature phase components obtained by the error signal detectors 19, 20 and the binary interference signals of the in-phase and the quadrature phase components.
More specifically, the error signals of the quadrature components of the main signal and the interference signal on the quadrature component are multiplied an exclusive OR gate 34 while the error signal of the in-phase component of the main signals and the interference signals on the in-phase component are multiplied by an exclusive OR gate 35. The signals obtained from these multiplications are analog-added by resistors 38, 39 and the output sum is integrated by an integrator 43. The bipolar attenuator 55 of in-phase in the quadrature amplitude modulator 51 is controlled using the output from the integrator 43.
In a similar manner to the above, the error signal of the in-phase component of the main signal and the quadrature phase component of the interference signal are multiplied by an exclusive OR 36 while the error signal of the quadrature phase component and the interference signal on the in-phase component are multiplied by an exclusive OR 37. The signals obtained by these multiplications are added to each other in analog by the resistors 40, 41, and integrated by the integrator 42. With the output from the integrator 42, the bipolar attenuator 54 of the quadrature phase in the modulator 51 is controlled.
FIG. 3 is a block diagram to show a third prior art device wherein a signal received on the main signal side and the received interference signal are detected in quadrature phase separately from each other, and the detector outputs are digitally processed unlike the first and the second prior art devices.
The signal received on the main signal side which have been converted into IF by a frequency converter 3 is input at a demodulator 12. In the demodulator 12, the local frequency 13 reproduced from the received signal on the main signal side is input at phase detectors 15, 16 to detect quadrature phase signals. The output from the detectors are passed through low-pass filters 17, 18 and taken out as base band signals of the in-phase and the quadrature phase.
Meanwhile, the interference signal converted into the IF band is input at phase detectors 27, 28 and detected in the quadrature phase by means of the local frequency 13 reproduced from the main signal. The outputs detectors are passed to low-pass filters 29, 30 to be taken out as the base-band signals of the in-phase and the quadrature phase.
The base-band signals of the received main signal and interference signal in respective in-phase and quadrature phase components are digitized by analog/digital converters 70 through 73 having a sufficient quantization precision. In this example, the analog/digital converters are used to exemplify digital processing.
In the case where the main signal is the signal of 16QAM, the outputs from analog/digital converters 70 through 73 are quaternary. Therefore, in order to output the error digital signals, they should be sampled by analog/digital converters having a precision of at least 3 bits. As shown in the table, binary signals are obtained to show the result of decision in the most and next bits and the direction of errors in the third bit. The sampling signal of the analog/digital converters 70 through 73 is clock signal 44 reproduced from the signal received on the main signal side.
The digitized interference signals in the in-phase and the quadrature phase components are input at bipolar attenuators 74 through 77 to eliminate the interference signal components mixed in the received signal on the main signal side by adders 78 through 81. The correlation between the error signals and the interference signals remaining in the main signals are obtained, and bipolar attenuators 74 through 77 are controlled in a manner to minimize the effect thereof.
More specifically, the polarity signal of the interference signal on the quadrature phase side (obtainable from the most significant bit of the analog/digital converter) is multiplied with the error signal of the main signal on the quadrature phase side by an exclusive OR 82, and the output therefrom is digitally integrated by an integrator 86 to control with the output thereto the bipolar attenuator 76 connected to the side of the quadrature side interference signal. An exclusive OR 83 multiplies the polarity signal on the quadrature side of interference signals with error signal of the main signal on the in-phase side, and the output therefrom is integrated digitally by an integrator 87 to control a bipolar attenuator 74 connected to the quadrature side of the interference signal. An exclusive OR 84 multiplies the polarity signal of interference signal on the in-phase side with the error signal of main signal on the in-phase side, and the output therefrom is integrated digitally by an integrator 88 to control with its output a bipolar attenuator 75 connected to the interference signal on the in-phase side. An exclusive OR 85 multiplies the polarity signal of the interference signal on the in-phase side with the error signal of the main signal on the quadrature side, and the output therefrom is digitally integrated by an integrator 89 to control a bipolar attenuator 77 connected to the in-phase side of the interference signals.
A problem exists in these prior art circuits in that the signals which cause the interference signal. This makes it necessary to install an auxiliary antenna for the sole purpose of receiving the signal which causes the interference. Also, when the main signal and the interference signal component share the same transmission path, the signals which cause interference cannot be precisely detected, and the interference signal component cannot, therefore, be completely eliminated.
This invention aims to solve those problems encountered in the prior art and to provide an interference cancellation circuit which can sufficiently eliminate and cancel an interference signal component even when the signal which causes the interference cannot be obtained directly.